The present invention relates to a display device, and, more particularly, to an active matrix type display device thereof.
In an active matrix type liquid crystal display device, pixel regions are formed on a liquid crystal side surface of one of a pair of substrates, which are arranged so as to face each other in an opposed manner, with a liquid crystal being disposed therebetween. The pixels are formed as regions which are surrounded by gate signal lines that extend in the x direction and are arranged in parallel in the y direction and drain signal lines that extend in the y direction and are arranged in parallel in the x direction.
Each pixel region is provided with a thin film transistor, which is operated upon receiving a scanning signal from one gate signal line, and a pixel electrode to which video signals from the drain signal line are supplied through the thin film transistor.
This pixel electrode generates an electric field between the pixel electrode and a counter electrode which is formed on the other substrate side, for example, and the light transmittivity of the liquid crystal disposed between these electrodes is controlled by this electric field.
Such a liquid crystal display device is provided with a scanning signal driving circuit, which supplies scanning signals to respective gate signal lines and a video signal line driving circuit which supplies video signals to respective drain signal lines.
In view of the fact that the scanning signal driving circuit and the video signal line driving circuit are constituted of a large number of MIS transistors having a constitution similar to that of the thin film transistors formed inside of the pixel regions, a technique has been employed in which semiconductor layers of these respective transistors are formed of polycrystalline silicon (p-Si), and the scanning signal driving circuit and the video signal line driving circuit are formed on a surface of one substrate along with the formation of the pixels.
The scanning signal driving circuit is a circuit which mainly uses a shift register, and the video signal line driving circuit also uses a shift register at a portion thereof. However, there has been a recent demand for a shift register which can be operated at high speed at a low voltage and with a low power and which has no through-current. To meet this demand, a shift register which is referred to as dynamic ratio shift register has been proposed, for example.
A dynamic ratio shift register of the type mentioned above has been disclosed in Japanese Patent Publication No. 45638/1987, for example, and the constitution thereof is illustrated in FIG. 9A. Further, FIG. 9B shows a timing chart of the circuit shown in FIG. 9A, which timing chart shows respective outputs VN1 and VN6 at nodes N1 and N6 corresponding to an input pulse φIN and synchronous pulses φ1, φ2.
First of all, when the synchronous pulse φ1 is changed from a Low level (referred to as “L” hereinafter) to a High level (referred to as “H” hereinafter) at the time t1, the input pulse φIN becomes “H”, and, hence, the potential VN1 of the node N1 is changed from “L” to “H” through a transistor NMT1.
Assuming the “L” state of the input pulse φIN and the synchronous pulses φ1, φ2 having inverse phases from each other as a ground level (GND), and the “H” state of the input pulse φIN and the synchronous pulses φ1, φ2 as a threshold value Vth of Vφ<NMT1, the potential VN1 at this point of time can be substantially expressed by the following equation (1). Here, Vφ indicates the voltage at the “H” level of the synchronous pulses φ1, φ2 and NMT1 indicates a MOS transistor.VN 1=Vφ−Vth  (1)
Even when the synchronous pulse φ1 falls from “H” to “L” at the time t2, the input pulse φIN remains at the “H” level, and, hence, the output VN1 holds the voltage expressed by the equation (1). In a strict sense, at a point of time at which the synchronous pulse φ1 falls, the potential becomes lower than the voltage expressed by the equation (1) due to a capacitive coupling between a gate of the transistor NMT1 and the node N1 or the like. However, such a phenomenon is not essential in the explanation of the operation, and, hence, the phenomenon is ignored. Since the transistor NMT1 turns OFF, the node N1 becomes a floating node.
Subsequently, when the synchronous pulse φ2 is changed from “L” to “H” at the time t2, provided that the following equation (2) is satisfied,Vφ−Vth3 Vφ  (2)The MOS transistor NNT2 turns ON and the pulse φ2 enters the node N2. At this point of time, due to the coupled capacitance Cbl, which is referred to as a bootstrap capacitance that is inserted between the nodes N1 and N2, a voltage rise on a point of the node N2 is transmitted to the node N1 which is in the floating state, so that the potential of the node N2 also rises.
Assuming that the rising potential of the node N2 is AVN2, the output VN1 is given by a following equation (3):VN1=(Vφ−Vth)+ΔVN2(Cb/Cb(Cb+Cs))  (3)
Here, the capacitance Cb includes, besides the capacitance shown in the circuit diagram, such as the preceding coupled capacitance CB1, all of the coupled capacitance of synchronous pulse φ2 and the node N1, which include the capacitance generated by the gate, the drain and the source of the transistor NMT2, or an inversion layer (channel) formed below the gate, and further include the direct connection capacitance between the wiring of the synchronous pulse φ2 and the node N1. Further, Cs indicates a capacitance obtained by subtracting the above-mentioned bootstrap capacitance Cb from the whole capacitance of the node N1 and constitutes the so-called parasitic capacitance.
Here, provided that the following equation (φ is satisfied at ΔVN2 Vφ.(Vφ−Vth)+Vφ(Cb/Cb(Cb+Cs))>Vφ+Vth  (4)This implies that the gate voltage of the MOS transistor NMT2, that is, the output VN1, becomes higher than Vφ+Vth. Accordingly, the output VN2 can be set to the potential of the voltage Vφ. By suitably selecting the capacitance Cb1, which constitutes a design element, it is easy to satisfy the above-mentioned equation (4), and, hence, the output VN2 can be set to the potential of the voltage Vφ.
Here, at the same time, the potential of the node N3 takes a value expressed by a following equation (5) through a MOS transistor NMT3, which is subjected to the diode connection.VN3=VφVth  (5)Since the MOS transistor NMT3 is subjected to diode connection, even when the synchronous pulse φ2 is changed from “H” to “L” at the time t3, the state expressed by the above equation (5) can be held.
When the synchronous pulse φ1 is changed from “L” to “H” at the time t3, an operation similar to that expressed by the equation (3) occurs at the node N3 and the MOS transistor NMT 5, so that the outputs VN3, VN4 respectively generate the change of potential as schematically shown in FIG. 1B.
Here, when the nodes N2, N4, N6 are used as output nodes, shift pulses (VN2, VN4, VN6) having a potential equal to that of the “H” level of the synchronous pulse can be obtained, and a dynamic operation which does not generate a through-current can be performed, as apparent from the above-mentioned operations.
However, when the dynamic ratio register having such a constitution is formed by directly providing MIS transistors having semiconductor layers which are made of polycrystalline silicon (p-Si) to surfaces of substrates (glass substrates) which are arranged to face each other in an opposed manner through a liquid crystal, it has been confirmed that the dynamic ratio register operates in an extremely unstable manner, so that a countermeasure to cope with such a phenomenon is needed.
That is, the capacitance, when the floating nodes, such as N1, N3, are at the “L” level, is extremely small, and the other capacitance of the nodes N1, N2, including Cdg1, Cdg2, is, as shown at Cdg1, Cgg2 of FIG. 9A, extremely small compared to the coupled capacitance between the synchronous pulse and the drain gates of the nodes Ni, N3. Hence, there exists a high possibility that unselected transistors also will be turned “ON”. When the circuit remains as it is, the design and the operational voltage are considerably restricted for holding the “OFF” state.
With respect to a monocrystalline semiconductor at the dynamic ratioless shift register which are made of thin film transistors formed on the glass substrate, the main reasons why the capacitance becomes very small when the floating node is at the “L” level are as follows.
FIG. 10A is a cross-sectional schematic view of an n-type MOS transistor formed on a monocrystalline semiconductor. A semiconductor integrated circuit having a substrate which constitutes the semiconductor is generally used in a form in which it is biased (including the case that it is grounded) for element separation or the like.
Accordingly, as shown in FIG. 10A, through a depletion layer capacitance Csw due to an inverse bias between a source (a diffusion layer) and a well (or a substrate), a depletion layer capacitance Cdw between a drain and the well and a capacitance Cgw between a gate and the well, the source, the drain and the gate are capacitively coupled with the well. Further, the wiring is also capacitively coupled with the substrate or the well which is disposed immediately below the winding with the capacitance Clw through a thick insulation film. These capacitance belong to a group of capacitances which are usually called parasitic capacitances.
Accordingly, at a portion of the node N3 shown in FIG. 9A, a large coupling capacitance with the well can be obtained due to the capacitance Csw of the NMT3 (Csw3), the capacitance Cgw of the NMT6 (Cgw6), the capacitance Cdw (Cdw6), the capacitance Csw of the NMT7 (Csw7) and the capacitance Clw (Clw3) of the wiring which constitutes this node.
Further, by making the bootstrap capacitance have the enhanced MOS capacitive constitution which is shown in FIG. 10B and FIG. 10C, the well is capacitively coupled with an inversion layer that extends from a depletion layer which constitutes a separate node at the “ON” time, as shown in FIG. 10B so that an efficient bootstrap effect (a boosting effect) is obtained, while a coupled capacitance Cb1 (w) with the well is obtained at the “OFF” time, as shown in FIG. 10B.
Accordingly, when the node N3 is at the “L” level, even when the node N3 is floating on the circuit shown in FIG. 9A, the large capacitance can be ensured with the bias of the well through the above-mentioned coupled capacitance. With respect to the capacitance, the sum of Cdw of the NMT3 (Cdw1) and the space capacitance C1 φ1 between the wiring of φ1 and the node N3 is sufficiently small, and, hence, the potential difference ΔVN3 of the node N3 when the wiring φ1 is changed from “L” to “H” is substantially expressed by the following equation (6).ΔVN3=Vφ×(Cdw+C1 φ1)/(Cdw1|C1φ2+Csw3+Cgw6+Cdw6+Csw 7+Cb1(w))  (6)
Further, as explained above, since the relationship expressed by the following equation (7) is established,Cdw1+Cφ2<<Csw3+Cgw6+Cdw6+Csw1+Cb1(w)  (7)it becomes easy to satisfy the following equation (8).ΔVN3<Vth  (8)However, when a similar circuit made of monocrystalline thin film transistors is formed on a glass substrate, the above-mentioned operation is not achieved.
FIG. 10D is a cross-sectional schematic view of the monocrystalline thin film transistor which is formed on the glass substrate. Provided that the substrate is formed of an insulating body, once a p layer arranged below a source, a drain or a gate becomes floating, the capacitance which can be coupled becomes the depletion layer capacitance Cdp, Csp between the source, or drain or the gate and the p layer arranged below the source, the drain or the gate or the small space capacitance Cs1, Cp1, Cd1 between the p layer and the wiring which is disposed so as to be remote from the source, drain or the gate. To take a portion of the node N3 of the circuit shown in FIG. 9A as an example, in the same manner as the above-mentioned example, the node N3 is capacitively coupled with the node N2 through the source Csp3 of the MOS transistor NNT3. Since the node N2 is also floating, the path is divided into a path which brings about the capacitive coupling with the node N1 through the capacitance Cb1 and a path which brings about the capacitive coupling with the synchronous pulse φ2 through the SP2 of the MOS transistor NMT2. Since the node N1 is also floating, the path is divided into a path which brings about the capacitive coupling with the input pulse φIN through the capacitance Csp1 of the MOS transistor NMT1 and a path which brings about the capacitive coupling with the ground potential Vss through the capacitance Csp4 of the MOS transistor NMT4, which brings about the capacitive coupling with the synchronous pulse φ1 through the capacitance Csg1 of the MOS transistor NMT1.
That is, both capacitances also become very small and the coupling with the synchronous pulse φ1 functions in such a manner that the output VN3 is boosted when the synchronous pulse φ1 becomes “L”  “H”.
Although the source of a MOS transistor NMT7 is capacitively coupled with the ground potential VSS through the capacitance Csp7, this is also not significant. Further, the node N3 is capacitively coupled with the node N4 through the capacitance Cb2 so that the node N4 is also floating. The wiring which constitutes the node N3 does not have the capacitance immediately below the node N3, and the node N3 has only a weak capacitive coupling with any one of the wirings through the space capacitance.
The node N3 is capacitively coupled with the synchrous pulse φ1 through the capacitance Cdg5 of the MOS transistor NMT5. This capacitive coupling is the direct capacitive coupling with the outside and is relatively large. This capacitance becomes a cause of instability.
Assuming the total sum of the above-mentioned other secondary coupled capacitance of the node N3, except for the capacitance Cdg5 as the capacitance CN3, the change of potential AWN3 of the node N3 when the synchronous pulse φ1 is changed from “L”  “H” is substantially expressed by a following equation (9). Since the capacitance CN3 is not so large as mentioned above, depending on values of the voltage Vφ and the capacitance Cdg5 (W size design of the MOS transistor NMT5 or the wiring layout of the synchronous pulse φ1), conditions shown by the following equation (10) are easily brought about.ΔVN3=Vφ×(Cdg5/(Cdg5+CN3))  (9)ΔVN33Vth  (10)
Once the conditions indicated by the above equation (10) are satisfied, the capacitance Cgp of the MOS transistor NMT5 (the capacitance with the inversion layer) and the bootstrap capacitance Cb2 are changed to the coupled capacitance with the node N3 and the φ1 in an opposed manner, so that the possibility that the MOS transistor NMT3 turns completely “ON” due to the bootstrap effect is extremely increased. That is, an unstable operation is generated such that nodes which are irrelevant to the node under control become “H” and generate outputs or start the scanning from such portions.
The present invention has been made in view of such a circumstance, and it is an object of the present invention to provide a display device having a dynamic ratioless shift register which ensures stable operation and which can increase the degree of freedom of design.